In a flip-chip mounting method in which a semiconductor bare chip is directly mounted on a circuit board, the present invention relates to a method of bump inspection for performing two-dimensional inspection by image processing of the external appearance of stud bumps of a two-level projecting shape formed on the electrode pad of a semiconductor bare chip.
In recent years, miniaturisation and weight reduction of electronic devices is being demanded; concomitantly with this, with the object of raising electronic circuit mounting densities, the flip-chip mounting method has come to be widely employed, in which semiconductor bare chips obtained by dividing a wafer into individual chips are turned over and directly mounted on a circuit board. For example, the flip-chip mounting method is currently being used to manufacture CSPs (Chip Size Packages) which are packaged with the same dimensions as the semiconductor bare chip and also MCMs (Multichip Modules), in which a plurality of semiconductor bare chips are mounted on a circuit board, and production of these continues to increase.
In the SBB (Stud Bump Bonding) method, which is one type of flip-chip mounting method as described above, bumps are formed on the electrode pad of a semiconductor bare chip by applying the wire bonding method and leveling is performed by a leveling device so as to make the heights of the bump heads of these bumps uniform, thereby forming stud bumps of a two-level projecting shape having a bump pedestal and bump head. In order to ensure the required quality at the flip-chip joint in subsequent processing steps, it is indispensable to inspect the external appearance and shape of the stud bumps that are thus formed. In this external appearance inspection, it is demanded that not just the position, shape and dimensions of the bump pedestal be inspected but also that the position, shape and dimensions of the bump head, respectively, are within allowed values; a function for measuring the respective position, shape and dimensions of the bump pedestal and bump head is therefore demanded.
As a method of automatically inspecting the external appearance of stud bumps, there is already known a technique (see Early Japanese Patent Publication No. H.4-56246) of ascertaining the quality by image processing of a composite signal obtained by picking up an image of a stud bump on the electrode pad by using an inspection camera. The image processing device that is employed for this has functions such as measurement of the dimensions of stud bumps and obtaining the long side and short side of arbitrarily shaped circumscribed rectangles and is thereby capable of recognising when a bump is not formed on an electrode pad. Also, the measurement results are compared with numerical values that are set beforehand by means of a central processing unit, and the quality of the stud bump is assessed in accordance with the result of this comparison.
However, with the method of inspection of the external appearance of stud bumps by image processing as described above, various problems remain that need to be solved for practical implementation. First of all, in measuring the shape and/or dimensions of a subject stud bump by image processing, it is necessary to separate the stud bump and a pattern surface of the semiconductor bare chip that is its background, by converting the image to binary form; however, with the prior art image processing technique, there is a problem that it is difficult to determine a binary conversion level such that accurate separation can be achieved of the pattern surface of the semiconductor bare chip and the bump pedestal and between the bump pedestal and bump head, respectively.
For example, if the binary conversion level is set so as to suit measurement of the bump head, measurement precision in measurement of the bump pedestal is adversely affected. On the other hand, if the binary conversion level is set such as to suit measurement of the bump pedestal, measurement precision in measurement of the bump head is adversely affected. That is, using the prior art image processing technique, the bump pedestal and bump head cannot both be measured with high measurement accuracy. Also, if the binary conversion level is set so as to suit measurement of the bump head, precise measurement of the bump pedestal, may be made impossible by the effect of noise produced by probe scarring during chip examination and present on the electrode pad and/or outline of the electrode pad. In such cases, there is a high risk of oversensitive assessment in which good stud bumps are assessed as bad or of mis-assessment in which bad bumps are assessed as being good.
Also, in the case of stud bumps of a shape in which the outline of the bump head is adjacent to the outline of the bump pedestal, the margin for setting the binary conversion level becomes small, so if the binary conversion level is inappropriate, due to, for example, fluctuations of the illuminance on the semiconductor bare chip during image pick-up, on binary conversion, a binary image is obtained in which the bump head and the chip pattern surface are linked, making it impossible to measure the bump head. In such cases, oversensitive assessment in which good bumps are evaluated as being bad is likely and the reliability of the inspection is low.
Secondly, in the forming of stud bumps, pillar offset defects may occur in which the respective centers of gravity of the bump pedestal and bump head are offset due to buckling of the bonding wire, or standing-wire defects may occur in which the tip of the wire may become erect due to a joining defect or tearing defect in the second bonding step. Such semiconductor bare chips cause product defects due to short-circuiting between the electrodes when these are installed, so pillar offset defects or standing-wire defects must be detected and excluded. However, using the prior art image processing technique, since only a long side and a short side of the circumscribed rectangle of the stud bump are found and inspected, it is difficult to improve the detection rate of such pillar offset defects and/or standing-wire defects.